Technical Field
Embodiments of the present disclosure relate generally to electronic circuits, and more specifically to a method of reference clock re-timing scheme for use in electronic circuits.
Related Art
There are several electronic circuits or components in which a reference clock is used to perform an operation such as, for example, reading the contents of a register. Phase detectors and time-to-digital-converter-based analog to digital converters (ADC) are some examples of such electronic circuits.
Phase detectors are commonly used in phase locked loop (PLL) circuits to generate an error signal representing a phase difference between a reference clock and an output clock of the PLL. In one phase detector implementation, a digital phase detector (PD) generates the phase error by computing a difference between a reference phase and an estimated phase. The reference phase is represented by a pre-determined number that equals the number of cycles (including a fractional portion of a cycle) of the output clock expected at each active edge of the reference clock. The estimated phase is represented by a number measured as the actual number of cycles of the output clock measured at the corresponding active edges of the reference clock. The reference phase and the estimated phase are measured from the start of commencement of the phase detector operation.
Typically, the determination of the estimated phase involves reading, at a clock edge of the reference clock, a count value registered in a counter clocked by the output clock. The reference clock and the output clock may be asynchronous with respect to each other. Therefore, the counter may be updating its count value when being read at a clock edge of the reference clock, thereby potentially resulting in a wrong count value being read due to metastability issues. Similar metastability issues may arise in time-to-digital-converter-based ADCs as well.
A reference clock re-timing scheme refers to a technique for generating a phase-shifted reference clock (i.e., a re-timed reference clock) to perform the operations (e.g., reading the contents of a counter) otherwise performed by the non-retimed reference clock, and to thereby avoid the metastability issues noted above.